Core Timing Concepts in Digital Circuit Design

Introduction

As an FPGA design engineer, I want to emphasize the crucial role of timing analysis in digital design. However, sometimes, we can compromise on some design aspects; timing analysis is non-negotiable and must meet our requirements. In the world of digital circuit design, there are two types of timing analysis: static timing analysis (STA) and dynamic timing analysis (DTA).

Based on my experience, nowadays in all digital designs, Static Timing Analysis is essential to ensure that the circuit will work correctly in all conditions at the required speed. In this article, I will explain some important aspects of Static Timing Analysis, which are crucial when working with STA tools.

Essential Timing Windows of Setup and Hold Time

Setup time and Hold time are two basic and simple definitions in static timing analysis. However, as far as I remember, most of the problems in static timing analysis happen when one of these two is violated in a design. I will explain these definitions below.

In digital designs, each flip-flop has specific timing requirements. The most important one is that data must remain stable during a specific time window in relation to the edge of a clock, which data will be captured on that edge, so then flip-flop capture and latch the data correctly. If data changes during this time window, the output of the flip-flop will become unpredictable or metastable. Boundaries of this timing window are known as setup and hold time.

• Setup Time: This is the minimum amount of time that data should be stable before the edge of the clock so that the flip-flop captures the data correctly.
• Hold Time: This is the minimum amount of time that data should remain stable after the edge of the clock so that the flip-flop can latch the data correctly.

The following figure illustrates both the setup time and hold time in relation to the edge of the clock.

Must-Know Timing Analysis for Digital Designers

In this section, I’ll dive into key analyses that I believe every digital design engineer should master.

1. 1. Maximum Clock Frequency with Setup Time Analysis: To Calculate the Maximum Clock Frequency of our Circuit, we should do a setup time analysis on the critical path of our circuit. The critical path includes the combinational logic with maximum delay in our circuit. Consider that the figure below is our critical path.

   

   In this figure, to avoid violating setup time, we should follow the equation below, which guarantees that data will arrive at flip-flop2 before setup time.

   

   The equation indicates that the data arriving at flip-flop2 is subject to three main delays: first, there is the clock skew of flip-flop one; next is the delay of flip-flop one between when it receives the clock edge and when it latches the data; and finally, the significant delay of the combinational logic. The sum of these delays should be less than the sum of the period of the clock, plus the clock skew of flip-flop two and subtracting the setup time which ensures data arrives at least setup time sooner than the edge of clock to next flip-flop. The left-hand side of this equation is known as the data arrival time, and the right-hand side is known as the setup time data required time. STA tools report setup slack as the difference between data required time and data arrival time, which should always be a positive value.

   

   In the worst case, the setup time slack can be zero. In this scenario, we have the maximum operating frequency of our circuit, which will be:

   

2. 2. Hold Time Analysis: In the previous figure, to avoid violating hold time, we should satisfy the following equation:

   

   This equation indicates that data will remain stable at least for hold time after the edge of the clock reaches the flip-flop. As in the previous section, the left-hand of this equation is the data arrival time, and the right-hand of this equation is known as the hold time data required time. STA tools report the difference between these two values as hold time slack, which should always be positive.

   

3. 3. Timing Path Exceptions: Not all paths in a digital design follow the default setup and hold behavior assumed by the STA tool. If certain paths are designed to operate differently, I need to specify them as timing exceptions. Otherwise, the STA tool might mistakenly flag these paths as having timing violations. There are typically three types of timing path exceptions:

   • False Paths: are paths that, due to the specific logic of the design, will never actually be used in normal operation.
   • Multicycle Pathsare paths intentionally designed to take more than one clock cycle to transfer data from the launch point to the capture point.
   • Minimum or Maximum Delay Pathsare paths where I need to set a specific delay constraint, defining how fast or slow the data should travel through that path.

   By carefully analyzing and managing normal timing paths and exceptions, I can ensure that the design meets all its timing requirements and operates reliably within the specified constraints.

4. 4. Clock Domain Crossing (CDC): In my experience, I cannot recall any digital design with only one clock domain. Most digital circuits have more than one clock domain, meaning that one part of a circuit works with one clock and another part works with another. The issue arises when we need to transfer data from one clock domain to another; this is referred to as Clock Domain Crossing (CDC). When a part of a circuit receives input from a different clock domain, it becomes metastable, as it is asynchronous for this clock domain, violating the setup time and hold time of this part of the circuit, ultimately causing metastability.

   There are numerous methods for investigating CDC, and a comprehensive exploration of it requires extensive discussion. However, I would like to explain two simple ways to address CDC issues in your circuits. The first approach is called a synchronizer circuit, used when transferring a single bit value from one clock domain to another. In this case, placing two back-to-back flip-flops in your destination clock for capturing the data significantly reduces the probability of metastability. Increasing the number of flip-flops further decreases the probability of metastability. In most cases, you can assume that the output of 4 flip-flops is not metastable and can use it. The following figure depicts the 2-flip-flop synchronizer circuit.

   

   When dealing with multiple bits, a synchronizer circuit is not suitable. In such cases, using an Asynchronous FIFO is one possible solution. This type of FIFO allows you to write data with one clock and read data with another clock. Therefore, you can write data with the clock used for data transfer and then read the data with the clock intended for data capture, without encountering any metastability issues.

Conclusion

Comprehending timing analysis is essential for ASIC/FPGA design engineers to ensure the reliability and efficiency of digital circuits. Understanding setup and hold times, calculating maximum clock frequency, and managing timing exceptions are crucial for building robust designs. Additionally, effectively dealing with Clock Domain Crossing (CDC) is vital because of its complexities in multi-clock domain circuits. By mastering these analyses and techniques, we can guarantee that our circuits function correctly under all circumstances, meeting the required speed and functionality standards. Timing analysis and CDC management are not merely routine checks; they are pivotal in ensuring our digital designs' success.